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Journal Articles Journal of Systems Architecture Year : 2012

Embedded system for contrast enhancement in low-vision

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Abstract

This paper presents a real-time contrast enhancement system, implemented in FPGA and adapted to display the processed images on a Head Mounted Display (HMD). A novel visual processing scheme is proposed which combines a version of the algorithm known as Contrast Limited Adaptive Histogram Equalization (CLAHE) with a spatial filtering based on a bio-inspired retina model. The system is designed so that visually impaired people can improve their functionality in environments with non-uniform lighting or with abrupt changes in lighting conditions. The parallelism offered by FPGA devices allow to achieve real-time processing with VGA-resolution images, reaching up to 60 frames per second. This system, developed on a FPGA of reduced complexity, has been compared in performance with a parallel implementation on a portable platform based on GPU.
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Dates and versions

inserm-03390812 , version 1 (21-10-2021)

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P Martínez Cañada, C Morillas, R Ureña, J M Gómez López, F J Pelayo. Embedded system for contrast enhancement in low-vision. Journal of Systems Architecture, 2012, 59, pp.30 - 38. ⟨10.1016/j.sysarc.2012.10.005⟩. ⟨inserm-03390812⟩

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